1. Field of the Invention
This invention relates to an on-chip clock distribution network having high speed due to a low resistance input protection network and with high capacitance output drive utilizing a CMOS ratioed buffer.
2. Prior Art
In digital computer system designs for clock distribution networks it is customary to employ three or more levels of inverting buffers which, of course, introduce various degrees of delay. Non-uniform delay variations in communicating transitions of the system clock to the processor chips by stable elements affect synchronism of the clock to a plurality of output loads. Input delay problems add to the foregoing, as do temperature, and frequency of operation is unduly limited by the number of delays. Also, processing of the wafers and radiation adversely affect clock delays from chip-to-chip. Usually, significant portions of the clock cycle is wasted in order to accommodate the worst case clock delay between chips and a synchronous computer system.
The present invention resolves these problems while minimizing receiver delay.